Micrel
MICRF405
April 2006
13
M9999-041906
(408) 955-1690
Data Interface and Data Transfer
Adr
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0000000
Mode1=0
Mode0=1
PA2=1
PA1=1
PA0=1
ClkOut_en=1
Sync_en=1
Load_en=1
0001100 LowBatt_level=0
LDO_by=0
LDO_en1=1 LDO_en0=1 MOD_LDc_en=0 PA_FEc_en=0 PA_LDc_en=0
LD_en=1
0001101 Bit_IO_en=1
Manchester_en=0 Sel_CRC1=1 Sel_CRC0=1 SyncID_Len1=0 SyncID_Len0=1 Pream_Len1=1 Pream_Len0=0
0011001 SyncID3_7=1
SyncID3_6=1
SyncID3_5=1 SyncID3_4=0
SyncID3_3=0
SyncID3_2=1
SyncID3_1=0
SyncID3_0=1
0011010 SyncID2_7=1
SyncID2_6=1
SyncID2_5=1 SyncID2_4=0
SyncID2_3=0
SyncID2_2=1
SyncID2_1=0
SyncID2_0=1
0011011 SyncID1_7=1
SyncID1_6=1
SyncID1_5=1 SyncID1_4=0
SyncID1_3=0
SyncID1_2=1
SyncID1_1=0
SyncID1_0=1
0011100 SyncID0_7=1
SyncID0_6=1
SyncID0_5=1 SyncID0_4=0
SyncID0_3=0
SyncID0_2=1
SyncID0_1=0
SyncID0_0=1
0011101
DATA_7
DATA_6
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
There are two main data interfaces; bit-wise and
byte oriented. The bit-wise interface use the DATAIN
(always input to the 405) and DATACLK pin (always
output from the 405). This interface is enabled with
the Bit_IO_en= 1 . If Sync_en=1 bit-wise
synchronous mode is selected and data clock is
provided on the RDY/DATACLK pin. In this mode,
the MICRF405 will sample the bit on the DATAIN pin
on the positive edge of the DATACLK. It is therefore
important that the MCU toggle the DATAIN pin on
negative edge of the DATACLK, See Figure 5. No
packet engine, CRC or Manchester encoding is
available in bit-wise data interface. To select
asynchronous mode set Sync_en= 0 . If VCO
modulation is selected, the DATAIN pin in tri-state
(MCU pin=input) until first bit is about to be
transmitted (see VCO modulation).
DATAIN
DATACLK
Figure 5. Synchronous Data Interface.
If Bit_IO_en=0, the byte wise interface is selected
and data is transferred byte wise through the one
byte buffer (register address 29). The register is
accessed the same way as the other register, as
explained in the previous sections. The only
difference is that it is instantly valid and do not need
any load pulse. This also applies to the SyncID
registers, address 25-28. When writing to address
29, the address counter will not increment which
means several bytes can be written into the buffer
without raising SEN and setting up a new write
session. The RDY/DATACLK pin will provide byte
synchronization. The data byte buffer is ready for
refill on falling edges on RDY. In this mode of data
transfer, Sync_en must be set.
The data in the buffer is fed into a packet engine
with an optional CRC calculation and Manchester
encoding. The virtual wire packet structure is shown
in Table 7. The preamble, SyncID field and CRC
field are automatically generated by the packet
engine. The user needs only to enter frame length
and payload for each packet. The preamble bytes
are equal to 10101010, and the number of preamble
bytes are given by 1+Pream_Len[1:0] (D1:D0
ControlRegister13). Next field is the SyncID which is
1-4 bytes long set by the SyncID_Len[1:0] bits. The
content of the SyncID bytes are fully programmable
and specified in the SyncID0-3 bytes. The SyncID0
byte, address 28, is sent first, and the SyncID3 byte,
address 25, is sent last. Refer to Table 8. The frame
length byte follows the SyncID field. It specifies
length of the payload and CRC. Finally, the CRC
field ends the packet. The SelCRC_0 bit specifies
the length of the CRC field. If it is set, a 2 byte ITU-T
CRC (start condition 00h) is calculated of the
payload and sent. If SelCRC_0=0, an 8 bit CCITT
CRC is calculated of the payload and sent. Either
two cases assuming SelCRC_1=1. If SelCRC_1=0,
no CRC is calculated on chip, and the user must
calculate this on the microcontroller and include it in
the payload. A Manchester encoder is available on
chip. It is activated if the Manchester_en bit is set. It
encodes the complete packet. The codes are 10
for 0 and 01 for 1 . The preamble byte is
automatically set 0 in this mode, as this will produce
the desired 10101010-pattern when Manchester
encoded. Note that on-the-air data rate will be twice
the bit rate set by the FSKClk_K/FSKn or
ASKClk_K/ASKn, which specifies the actual
throughput. Because of this, FSKn needs to be
greater than zero if VCO modulation is selected,
Modulation[1:0]<2.
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